Standard cells are used in order to speed up the design of a semiconductor chip. By way of example, standard cells are gates, shift registers or other digital or analog modules, which are formed from individual integrated components, such as transistors, diodes or resistors, and which generally provide one or more standardized functions. In addition to standard cells, other elements are normally also arranged on the semiconductor chips.
The standard cells are normally arranged in a plurality of mutually adjacent rows. The standard cells in one row are supplied with electrical power by means of tracks arranged along the row. The associated power supply tracks in each row are connected to one another and to further elements or connections of the semiconductor chip.
Furthermore, normally, further tracks are provided, in particular for transmission of analog or digital signals between the standard cells and into connections of the semiconductor chip. The tracks are arranged in one, or generally more, so-called metallization layers.
In order to arrange the tracks optimally, a so-called router program is used, which connects the inputs and outputs of standard cells to one another and to connections of the semiconductor chip. The respective position and/or the profile of the individual tracks are/is then disentangled in order to allow the standard cells and/or the tracks to be arranged as densely as possible and in order to allow as short a signal delay as possible. In addition to this known arrangement of standard cells and their wiring, further arrangement regulations, of course, such as a vertical or functionally related arrangement are feasible, for example in order to separate a digital area and an analog area on an ASIC or the like.
Place and route methods, by means of which standard cells can be placed and wired up, are known from the production of ASIC semiconductor components (ASIC: Application Specific Integrated Circuit).
In typical ASICs there are a large number (in comparison to memory design (for example, DRAM)) of metal layers available for wiring, so that the standard cells in ASICs can be placed very densely; there are no problems in connecting the cells to one another.
The use of standard cells can be particularly problematic in the case of memory components, since fewer metal layers are available, and the standard cell density that can be achieved is therefore considerably less. This results in the need for wiring channels transversely with respect to the direction of standard cell rows.